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Verification by Error Modeling Using Testing Techniques in Hardware Verification

Автор: Bo0mB0om » 12 февраля 2016
Verification by Error Modeling Using Testing Techniques in Hardware Verification

Verification by Error Modeling: Using Testing Techniques in Hardware Verification by Katarzyna Radecka, Zeljko Zilic
English | 2003 | ISBN: 1402076525 | 233 pages | PDF | 13,8 MB




This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.








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