Cadence SPB OrCAD 16.60.053 Hotfix | 1.6 GB
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 53 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry's first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.DATE
: 07-16-2015 HOTFIX VERSION: 053CCRID PRODUCT PRODUCTLEVEL2 TITLE
1045706 SIP_LAYOUT INTERACTIVE Enhance the Split Via command to be able to split a stacked via into multiple vias
1356381 ALLEGRO_EDITOR INTERFACE_DESIGN PCB Editor hangs when adding net to a net group
1416250 CONCEPT_HDL CORE Save hierarchy from TDO crashes DesignEntryHDL
1424166 ALLEGRO_EDITOR SHAPE Dynamic shapes will not fill using the zcopy command
1424853 ALLEGRO_EDITOR INTERFACES Error message "Failed to add (LW)POLYLINE" when importing DXF file into PCB Editor
1426668 ALLEGRO_EDITOR DRC_CONSTR Require shape DRCs with route keepout
1427168 F2B DESIGNVARI Variant directives don't get created in CPM while creating variants
1427481 PCB_LIBRARIAN IMPORT_TEXT To enhance the import txt file in the PDV
1428336 PCB_LIBRARIAN CORE Symbol Pin Property Attributes not editable with HF49
1430405 ALLEGRO_EDITOR MANUFACT Running Export - IPC-2581: The exported .xml data does not contain the Probe figures or the probe information
1431570 PCB_LIBRARIAN VERIFICATION PDV con2con should read additional properties like NC_PINS from part_table view independant on PACK_TYPE
1431591 ADW LRM LRM should be able to Autofix the parts with $PART_NUMBER even if the SYNC_PROPERTIES has a value of PART_NUMBER
1431875 APD EDIT_ETCH When trying to multi-route a group of nets, APD crashes with the .SAV error.
1434375 ALLEGRO_EDITOR INTERFACES Running Export - IPC-2581: The last or largest pin in a series of pins listed in pinOneCfg.txt is selected
1434975 ALLEGRO_EDITOR MANUFACT Running Testprep > Manual causes Allegro PCB Editor to crash
1435685 F2B PACKAGERXL Export Physical indicates 36 errors are found during backannotation, but the backannotate.log file contains no errors
1436206 SIP_LAYOUT ASSY_RULE_CHECK Ignore shapes autogenerated by the crosshatch void fill routine in the acute angle shape boundary ADRC check
1436699 CONCEPT_HDL INTERFACE_DESIGN model assignment not working if signal_model exists within a block
1436989 ALLEGRO_EDITOR OTHER PCB Editor crashes after pouring copper planes
1437150 APD DIE_GENERATOR Creating a die using the Compose from Geometry command gives error, "E-(SPMHA1-70): Pin is outside of the extents"
1437287 CONCEPT_HDL CHECKPLUS CheckPlus Segmentation Fault in LINUX
1437560 ALLEGRO_EDITOR OTHER APD crashes when running gloss with dielectric generation for the given testcase.
1437565 F2B DESIGNVARI Variant Hier BOM report puts Block DNI in wrong report section
1437725 APD EDIT_ETCH Route > Slide exhibits erratic behavior on differential pairs
1437748 SIP_LAYOUT INTERACTIVE Allegro Editor and APD have the command opengl report defined in the menu. Please add this to the SIP menu structure
1438933 CONCEPT_HDL CONSTRAINT_MGR Model Defined Differential Objects are named differently
1439104 ASI_SI SPDIF SPDIF popup window
1439574 CONCEPT_HDL CORE How do you rotate groups of objects in windows mode?
1440393 ALLEGRO_EDITOR INTERFACES Ability to extract STEP properties from DRA requested
1440589 ALLEGRO_EDITOR DATABASE Edit - Change crashes the database with errors.
1441665 CONCEPT_HDL CORE Property not annotated visible as set in ppt_optionset.dat
1441672 SIP_LAYOUT ASSY_RULE_CHECK ADRC Hangs and does not close
1441724 SIP_LAYOUT PLATING_BAR Need to be able to set the Plating Bar Width.
1442144 ALLEGRO_EDITOR SCRIPTS PCB Editor crashes when replaying script
1442798 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running dbdoctor
1443693 ALLEGRO_EDITOR SCRIPTS Change Accelerator keys for new OrCAD shape Menu
1443738 F2B DESIGNVARI Automatically exclude Nets or Ground Symbols from the Group while adding to Variant
1444066 CONCEPT_HDL CORE Replace parts in variant view crash DEHDL if cpm library list contains nonexisting libraries.
1444076 CONCEPT_HDL CORE Replacing parts in variants backannotates ALL injected properties in variant view
1444676 ALLEGRO_EDITOR SCRIPTS difference in PCB Editor and OrCAD PCB Editor menus in Hotfix 51About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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