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Cadence SPB OrCAD 16.60.059 - 17.00.005 Hotfix 15.10.15

Автор: rollroy » 15 октября 2015
Cadence SPB OrCAD 16.60.059 - 17.00.005 Hotfix 15.10.15

Cadence SPB OrCAD 16.60.059 - 17.00.005 Hotfix 15.10.15
Cadence SPB OrCAD 16.60.059 - 17.00.005 Hotfix | 2.08 GB


Cadence Design Systems, Inc., a leader in global electronic design innovation, has released the hotfix of Cadence Allegro and OrCAD 17.0 design solution with new features, enhanced customization capabilities, and simulation performance improvements that provide customers a shorter, more predictable path to product creation.
HOTFIX VERSION: 17.00.005



CCRID PRODUCT PRODUCTLEVEL2 TITLE

1260002 ALLEGRO_EDITOR INTERACTIV Symbols with ALT_SYMBOLS_HARD property are mirrored by Edit - Move - Mirror
1356381 ALLEGRO_EDITOR INTERFACE_DESIGN PCB Editor hangs when adding net to a net group
1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate
1394052 ALLEGRO_EDITOR INTERACTIV Edit Mirror preview is wrong
1412635 APD DATABASE APD crashes on saving design
1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation
1436070 SIG_EXPLORER SIMULATION Incorrect rise time for IBIS buffer when simulated in SigXplorer
1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
1441672 SIP_LAYOUT ASSY_RULE_CHECK ADRC Hangs and does not close
1443249 MODEL_INTEGRIT GUI Model Integrity does not show version number in QIR 9
1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor
1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board
1450135 ASI_SI OTHER Linked differential signal waveform of SigNoise report is not displayed in SystemSI viewer

HOTFIX VERSION: 16.60.059

CCRID PRODUCT PRODUCTLEVEL2 TITLE

1181942 SIP_LAYOUT ASSY_RULE_CHECK ADRC reports different results from the spacing set-up
1328452 ALLEGRO_EDITOR INTERACTIV When changing the shape type, Right-click - Next does not work for subsequent changes
1441502 GRE IFP_INTERACTIVE Design partition cannot be imported.
1457920 SIP_LAYOUT OTHER Wire Bond Import is not working correctly with discrete parts
1464865 CONCEPT_HDL CONSTRAINT_MGR For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
1467365 ALLEGRO_EDITOR OTHER Cadence cshrc for LINUX has an extra space in it.
1473744 ALLEGRO_EDITOR INTERACTIV The 'Chamfer' function does not work correctly if the second Trim Segment value is specified instead of the first.
1475599 SIP_LAYOUT SYMB_EDIT_APPMOD Refresh co-design die of an enlarged die is not placed correctly
1476284 CONSTRAINT_MGR OTHER Changes with Tpoint pairing not being propagated to the brd file
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown
1476855 ALLEGRO_EDITOR DATABASE Trying to import Netlist, getting SPMHNI-194 error
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
1478225 SIP_LAYOUT DIE_EDITOR IOP incorrectly rotates pins at a co-design die
1478465 SIP_LAYOUT WIREBOND Ability to set default bond wire option to on for wirebond import/export commands
1478994 SIP_LAYOUT SKILL axlUIMenuChange does not work on Linux
1479023 CONSTRAINT_MGR OTHER The cmDiff reports different data when files are reversed in UI
1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO
1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'
1480538 SIP_LAYOUT DIE_EDITOR CTE compensation is limited to 3 decimal places, can that be increased
1481109 APD MANUFACTURING control Package Design Integrity for snapping the via to pin
1482771 SIP_LAYOUT WIREBOND Fingers and wires cross when moving the guide path

Bit: x64
Home: www.cadence.com
Interface: english
OS: Wind0ws XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.056 - 17.00

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